Moore’s Law
They saw how the end of Moore’s Law meant that you could no longer easily squeeze more performance out of general purpose CPU cores. You needed specialized hardware: Coprocessors.
Speed
We are stuck on close to 3–5 GHz. Go higher and Watt consumption and heat generation goes through the roof. However we are able to add a lot more transistors. We simply cannot make the transistors work faster.
Low number of instructions
This is exactly what RISC-V got designed for. It has a bare minimum instruction-set of about 40–50 instructions which lets it do all the typical CPU stuff. It may sound like a lot, but keep in mind that an x86 CPU has over 1500 instructions.
Using less silicon
The small and simple instruction-set of RISC-V makes it possible to implement RISC-V cores in much less silicon than ARM.
Processor + Coprocessors
Every coprocessor will be different. It will thus contain a RISC-V processor to manage things which implements the core instruction-set as well as an extension instruction-set tailor made for what that co-processor needs to do.
ARM Processor + RISC-V Coprocessors
Ironically we may see a future where Macs and PCs are powered by ARM processors. But where all the custom hardware around them, all their coprocessors will be dominated by RISC-V. As coprocessor get more popular more silicon in your System-on-a-Chip (SoC) may be running RISC-V than ARM.
ARM + RISC-V, not ARM or RISC-V
I though the future would be about ARM or RISC-V. Instead it will likely be ARM and RISC-V.
Combining general purpose + specialized tasks
General purpose ARM processors will be at the center with an army of RISC-V powered coprocessors accelerating every possible task from graphics, encryption, video encoding, machine learning, signal processing to processing network packages.