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What Does RISC and CISC Mean in 2020?

date May 28, 2021
authors Erik Engheim
reading time 4 mins

How to chose an ISA? Power consumption and licensing

Well, it turns out all instruction sets are not created equal. The ISA of a CPU heavily influence how you can design the CPU itself. The particular ISA you use can complicate or simplify the job of creating a high performance CPU or a CPU that consumes little power. The second issue is licensing.

Specialised tasks

This is what Apple wants. They want to create tailor made solutions for their computers with specialized hardware handling things like machine learning, encryption and face recognition. If you go with x86 you have to do all that on external chips.


ARM vs x86

Instruction Set Architectures tend to follow different core philosophies for how the ISA is defined. x86 is what we call a CISC architecture. While ARM follows the RISC philosophy.

Instruction lengths

CISC instructions can in principle be any length. RISC instructions tend to be of fixed length.

How did RISC start winning?

RAM started getting cheaper, compilers got better and people were not programming as much in assembly code anymore. This change in the technological landscape caused the emergence of the RISC philosophy.

Compiler writers chosing simpler instructions

Compiler writers also found it hard to pick one of these complex instructions. Instead they preferred to combine simpler instructions to get the job done.

Writing compilers is easier than writing microcode

So the RISC idea was: Let us ditch the complex instructions and replace them with fewer simple instructions. Instead of debugging and fixing Microcode programs which is hard. You leave it to compiler writers to solve the issues.

Reduced == lower instruction complexity

There is some contention in what the word Reduced should be interpreted as in relation to RISC. It has been interpreted as reducing the number of instructions. But a more sensible interpretation is that it means a reduction in instruction complexity.

RISC design

Instruction and clock cycles

We could describe using the cash register as having a latency of 3 time units, but a throughput of one shopping per 1 time unit. In microprocessor terminology this would mean 1 instruction has a latency of 3 clock cycles, but an average throughput of 1 instruction per clock cycle.

Standardization of instruction and duration

RISC designers understood this. Thus they tried to standardize how long each instruction is and split up what an instruction does into stages which take roughly the same time. That way each resource inside the CPU can remain utilized to the max constantly as instructions get processed.

ARM RISC processor, it has a 5-stage pipeline for processing instructions:

  1. Fetch instruction from memory and update program counter to be able to fetch next instruction next clock cycle.
  2. Decode instruction. Meaning figure out what it is supposed to do. That means activating various electric wires to toggle on different parts of the CPU we are using to perform the instruction.
  3. Execute involves using the Arithmetic Logic Unit (ALU) or perform shift operations.
  4. Memory Access data in memory if relevant. That is what a load instruction would do.
  5. Write back results of previous operation to relevant register.

Complexity of CISC architectire

With CISC instructions is this tricky. Instructions can be variable length. So you don’t really know until you decode parts of the instruction where the next instruction will be. The second problem is that CISC instructions can have arbitrary complexity. Making multiple memory accesses and doing a whole host of things which means you cannot easily divide a CISC instruction into cleanly separate parts which can execute in a staged fashion.

Compressed instruction sets

Compressed instruction sets have been a game changer for RISC. Some RISC variants manage to use fewer bytes than x86 to for the same programs using this strategy.

Memory vs cache

This was the early RISC strategy when RISC programs took more memory than CISC programs. Because RISC CPUs were simpler, they required fewer transistors to implement. That left more silicon real-estate which could be used for other things such as cache. Thus by having larger caches RISC CPUs compensated for their programs being somewhat larger than CISC programs.

Pipelining bs creaking instructions into micro-ops

The RISC advantage still exists. CISC ISA instructions were not designed to be easy to pipeline. Hence breaking those instructions into micro-ops is a complex and messy task, that may not always work great.